The present invention generally relates to semiconductor memories, and more particularly to a semiconductor memory which has a reduced chip area required for an access circuit and is capable of operating at an improved operation speed.
Generally, in a semiconductor memory which is used in the field of image processing, there is a demand to enable both a random data access from a central processing unit (CPU) and a serial data access from a cathode ray tube (CRT). Hence, a so-called dual port memory which has a random access port and a serial access port is used in the field of image processing.
A conventional dual port memory comprises a random access memory (RAM) and a serial access memory (SAM) which is provided with a data register for holding a datum amounting to one word of the RAM. By making successive access to each cell of the data register, it is possible to make an access to the RAM via the SAM.
There are two methods of making access to the data register as will be described hereunder.
In FIG. 1, a decoder 1 decodes an address signal and sets "1" to one of registers constituting a pointer 2. The "1" set in the pointer 2 is successively shifted responsive to a clock signal received from a clock generator 3. The clock generator 3 generates the clock signal based on an external clock signal. Each register of the pointer 2 makes a pair with a corresponding memory cell of a serial access memory 4, and thus, an access is made to a memory cell of the serial access memory 4 corresponding to the position of "1" set in the pointer 2. A datum is read out from or written into the memory cell of the serial access memory 4 to which the access is made.
On the other hand, in FIG. 2, an address counter 5 generates a binary address signal and a predecoder 6 generates an internal address signal by converting the binary address signal into an octal address signal, for example. A decoder 7 decodes the internal address and makes access to a memory cell of a serial access memory 8. In other words, it is possible to successively make serial access to the memory cells of the serial access memory 8 by repeating a counting operation of the address counter 5 in response to the clock signal.
However, according to the first conventional method described in conjunction with in FIG. 1, it is necessary to provide the pointer 2 which comprises a number of registers equal to the number of memory cells of the serial access memory 4. For example, in a case where the RAM comprises an array of 512.times.512 memory cells, there are 512 memory cells in the serial access memory 4 and it is consequently necessary to provide 512 registers in the pointer 2. As a result, there is a problem in that the pointer 2 occupies a large area within the chip.
On the other hand, according to the second conventional method described in conjunction with in FIG. 2, the problem of the pointer occupying a large area within the chip is eliminated because no pointer is used. But the following circuit operation is required to make access to the serial access memory 8. That is, (i) the clock signal must be generated by the clock generator 3 responsive to the external clock signal, (ii) the address counter 5 must be operated in response to the clock signal, (iii) the binary address signal (binary datum) from the address counter 5 must be subjected to a data conversion in the predecoder 6, and (iv) the internal address signal from the predecoder 6 must be decoded in the decoder 7. As a result, it is difficult to increase the operation speed of the memory. The operating time of the predecoder 6 in particular is relatively long and greatly affects the operation speed of the entire memory.